The majority of present day integrated circuits are implemented by using a plurality of interconnected field effect transistors (FETs), also called metal oxide semiconductor field effect transistors (MOSFETs), or simply MOS transistors. A MOS transistor includes a gate electrode as a control electrode and spaced apart source and drain regions between which a current can flow. A control voltage applied to the gate electrode controls the flow of current through a channel between the source and drain regions.
In an integrated circuit fabrication facility, a plurality of different product types are usually manufactured at the same time, such as memory chips of different design and storage capacity, CPUs of different design and operating speed and the like, wherein the number of different product types may even reach a hundred and more in production lines for manufacturing ASICs (application specific ICs). Since each of the different product types may require a specific process flow, different mask sets for the lithography, specific settings in the various process tools, such as deposition tools, etch tools, implantation tools, chemical mechanical polishing (CMP) tools, metrology tools and the like, may be necessary. Consequently, a plurality of different tool parameter settings and product types may be encountered simultaneously in a manufacturing environment, thereby also creating a huge amount of measurement data, since typically the measurement data are categorized in accordance with the product types, process flow specifics and the like.
The measurement data for controlling production processes, such as lithography processes and the like, may be obtained by dedicated structures, which may be positioned within the die region of the semiconductor wafer if a corresponding area consumption of these structures may be compatible with the overall design criteria of the circuit layout under consideration. In other cases, the test structures may typically be provided in an area outside of the actual die region, which may also be referred to as a frame of the wafer, which may be used for dicing the substrate when separating the individual die regions. As used in the present disclosure, the term “active portion” of the integrated circuit refers to those portions of the die including the functional circuits that are used during standard operation of the integrated circuit, whereas the “test portion” refers to those portions including the aforementioned test structure and may include, for example, the frame. During the complex manufacturing sequence for completing semiconductor devices, such as CPUs and the like, an immense amount of measurement data may be created, for instance by inspection tools and the like, due to the large number of complex manufacturing processes, the mutual dependencies of which may be difficult to assess, so that, usually, factory targets may be established for certain processes or sequences, which are assumed to provide process windows to obtain a desired degree of final electrical behavior of the completed devices. That is, the complex individual processes or related sequences may be monitored and controlled on the basis of respective inline measurement data such that the corresponding process results may be maintained within specified process margins, which in turn may be determined on the basis of the final electrical performance of the product under consideration.
Consequently, in view of enhanced overall process control and appropriately targeting the various processes on the basis of the final electrical performance, electrical measurement data may be created on the basis of dedicated test structures that may be provided in the frame region in combination with appropriate probe pads formed in the metallization system at a very advanced manufacturing stage. These electrical test structures may comprise appropriate circuit elements, such as transistors, conductive lines, capacitors and the like, which may be appropriately connected to the probe pads so as to allow dedicated measurement strategies for assessing electrical performance of the various circuit elements in the test structure, which may then be related to the performance of the circuit elements in the actual die region. These electrical measurement data may include resistance values of conductive structures, threshold voltages of transistors, drive current capability of the transistors, leakage currents and the like, wherein these electrical characteristics may be influenced by the large number of manufacturing processes involved.
In order to ensure that the dedicated test structures accurately reflect the performance of the devices in the active portion of the integrated circuit, the same design rules are often used to fabricate both the devices in the active portion and the dedicated test structures. One such design rule, well-known in the art, is the “antenna rule” that is employed to prevent against the “antenna effect.” For example, in recent semiconductor process wiring steps, various plasma techniques have been used. The representative plasma techniques include dry etching at the wiring layer patterning, plasma TEOS film deposition of wiring layer insulating film in a multi-layered wiring step, and the like, for example, which will be hereinafter referred to as plasma steps. When plasma etching is executed, if a diffusion layer does not connect to metal wiring, plasma charges accumulate in the metal wiring and an electric current flows into the gate oxide film of the transistor to which the metal wiring connects. The current may potentially cause damage to the gate oxide film, change in the transistor characteristics because of film quality change of the gate oxide film, or degradation of the hot carrier life. Such phenomena are called “antenna effects,” and damage caused by the antenna effect will be hereinafter referred to as “antenna damage.”
To protect against antenna damage, countermeasures may be taken in accordance with various design rules that include the addition of a protection diode structure. As is known in the art, diodes only allow current to flow therethrough in one direction. If a protection diode is provided, plasma charges escape through a diffusion layer of the protection diode so that the occurrence of antenna damage is eliminated.
However, during certain testing procedures utilizing the testing structures, non-standard electrical biasing conditions are required for the electrical test structures. This especially happens in cases where negative gate bias has to be applied on NFETs or positive gate bias has to be applied on PFETs. Furthermore, depletion devices or zero-Vt devices regularly require opposite gate biasing. The inclusion of protection diodes in testing structures results in testing problems when opposite biasing conditions are required. That is, currently used protection diodes are not capable of operation under non-standard gate biasing conditions.
Accordingly, it is desirable to provide improved integrated circuits with testing structures that are operable under a broad range of testing conditions, including the application of both positive and negative biases. It is additionally desirable to provide integrated circuits that include test structures with protection diodes that are capable of operating under both positive and negative bias conditions. Furthermore, other desirable features and characteristics of the present disclosure will become apparent from the subsequent detailed description and the appended claims, taken in conjunction with the accompanying drawings and the foregoing technical field and background.